Routing Congestion in VLSI Circuits: Estimation and Optimization (Record no. 14636)

MARC details
000 -LEADER
fixed length control field 03723nam a22005055i 4500
001 - CONTROL NUMBER
control field 978-0-387-48550-8
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170628033321.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2007 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780387485508
-- 978-0-387-48550-8
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/0-387-48550-3
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.4
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJFC
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC008010
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Saxena, Prashant.
Relator term author.
245 10 - TITLE STATEMENT
Title Routing Congestion in VLSI Circuits: Estimation and Optimization
Medium [electronic resource] /
Statement of responsibility, etc by Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar.
264 #1 -
-- Boston, MA :
-- Springer US,
-- 2007.
300 ## - PHYSICAL DESCRIPTION
Extent XIV, 250 p.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
490 1# - SERIES STATEMENT
Series statement Series on Integrated Circuits and Systems,
International Standard Serial Number 1558-9412
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note The Origins of Congestion -- An Introduction to Routing Congestion -- The Estimation of Congestion -- Placement-level Metrics for Routing Congestion -- Synthesis-level Metrics for Routing Congestion -- The Optimization of Congestion -- Congestion Optimization During Interconnect Synthesis and Routing -- Congestion Optimization During Placement -- Congestion Optimization During Technology Mapping and Logic Synthesis -- Congestion Implications of High Level Design.
520 ## - SUMMARY, ETC.
Summary, etc With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware. Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design. Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer aided design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Telecommunication.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Systems engineering.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer-Aided Engineering (CAD, CAE) and Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Communications Engineering, Networks.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Shelar, Rupesh S.
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Sapatnekar, Sachin S.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9780387300375
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Series on Integrated Circuits and Systems,
-- 1558-9412
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://dx.doi.org/10.1007/0-387-48550-3">http://dx.doi.org/10.1007/0-387-48550-3</a>
912 ## -
-- ZDB-2-ENG
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Source of acquisition Total Checkouts Barcode Date last seen Price effective from Koha item type Shelving location Cost, normal purchase price Inventory number Full call number
    Dewey Decimal Classification     Central Library Central Library 28/06/2017 Springer EBook   E-37815 28/06/2017 28/06/2017 E-Book        
    Dewey Decimal Classification     Central Library Central Library 11/07/2017 ALLIED PUBLISHERS PVT LTD BANGALORE   G-10246 11/07/2017 11/07/2017 Reference VLSI 6086.96 5905 621.3815

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