MARC details
000 -LEADER |
fixed length control field |
03518nam a22005175i 4500 |
001 - CONTROL NUMBER |
control field |
978-1-4020-5546-1 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
DE-He213 |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20170628033501.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
100301s2007 ne | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781402055461 |
-- |
978-1-4020-5546-1 |
024 7# - OTHER STANDARD IDENTIFIER |
Standard number or code |
10.1007/978-1-4020-5546-1 |
Source of number or code |
doi |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK7888.4 |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TJFC |
Source |
bicssc |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TEC008010 |
Source |
bisacsh |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Nedjah, Nadia. |
Relator term |
author. |
245 10 - TITLE STATEMENT |
Title |
Co-design for System Acceleration |
Medium |
[electronic resource] : |
Remainder of title |
A Quantitative Approach / |
Statement of responsibility, etc |
by Nadia Nedjah, Luiza De Macedo Mourelle. |
264 #1 - |
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Dordrecht : |
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Springer Netherlands, |
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2007. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XIX, 229 p. |
Other physical details |
online resource. |
336 ## - |
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text |
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txt |
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rdacontent |
337 ## - |
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computer |
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c |
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rdamedia |
338 ## - |
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online resource |
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cr |
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rdacarrier |
347 ## - |
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text file |
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PDF |
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rda |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
The Co-design Methodology -- The Co-design System -- VHDL Model of the Co-design System -- Shared Memory Configuration -- Dual-port Memory Configuration -- Cache Memory Configuration -- Advanced Topics and Further Research. |
520 ## - SUMMARY, ETC. |
Summary, etc |
In Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer hardware. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Memory management (Computer science). |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer network architectures. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer science. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Systems engineering. |
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer Hardware. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer Systems Organization and Communication Networks. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Memory Structures. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Processor Architectures. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Mourelle, Luiza De Macedo. |
Relator term |
author. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Display text |
Printed edition: |
International Standard Book Number |
9781402055454 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/978-1-4020-5546-1">http://dx.doi.org/10.1007/978-1-4020-5546-1</a> |
912 ## - |
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ZDB-2-ENG |