MARC details
| 000 -LEADER |
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| fixed length control field |
03442nam a22004695i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-1-4020-6884-3 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20170628033516.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
100301s2008 ne | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781402068843 |
| -- |
978-1-4020-6884-3 |
| 024 7# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
10.1007/978-1-4020-6884-3 |
| Source of number or code |
doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Veenstra, Hugo. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Circuit and Interconnect Design for RF and High Bit-Rate Applications |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc |
by Hugo Veenstra, John R. Long. |
| 264 #1 - |
|---|
| -- |
Dordrecht : |
| -- |
Springer Netherlands, |
| -- |
2008. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
XII, 246 p. |
| Other physical details |
online resource. |
| 336 ## - |
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| -- |
text |
| -- |
txt |
| -- |
rdacontent |
| 337 ## - |
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| -- |
computer |
| -- |
c |
| -- |
rdamedia |
| 338 ## - |
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| -- |
online resource |
| -- |
cr |
| -- |
rdacarrier |
| 347 ## - |
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| -- |
text file |
| -- |
PDF |
| -- |
rda |
| 490 1# - SERIES STATEMENT |
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| Series statement |
Analog Circuits And Signal Processing Series |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
The Challenge -- Interconnect Modelling, Analysis and Design -- Device Metrics -- Cross-Connect Switch Design -- Bias Circuits Tolerating Output Voltages Above BVCEO -- Design of Synchronous High-Speed CML Circuits, a PRBS Generator -- Analysis and Design of High-Frequency LC-VCOs. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the ‘interconnect’) and circuit design. Circuit and Interconnect Design for RF and High Bit-rate Applications covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are ‘first-time right’. A thorough analysis of the interplay between on-chip circuits and interconnects is presented, including practical examples in high bit-rate and RF applications. Optimum interconnect geometries for the distribution of RF signals are described, together with simple models for standard interconnect geometries that capture characteristic impedance and propagation delay across a broad frequency range. The analyses also cover single-ended and differential geometries, so that the designer can incorporate the effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part. From the technology perspective, transistor performance and its relationship to design targets for high bit-rate and RF applications is extensively discussed. Traditional figures of merit, such as fT and fmax and their relevance to circuit design are discussed, and new figures of merit are introduced that are shown to be highly valuable for broadband circuit and oscillator design. In addition, an analysis of transistor operation at supply voltages above breakdown voltage BVCEO, is presented. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Processor Architectures. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Long, John R. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9781402068829 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Analog Circuits And Signal Processing Series |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/978-1-4020-6884-3">http://dx.doi.org/10.1007/978-1-4020-6884-3</a> |
| 912 ## - |
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| -- |
ZDB-2-ENG |
