MARC details
| 000 -LEADER |
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| fixed length control field |
03259nam a22004695i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-1-4020-8363-1 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20170628033520.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
100301s2008 ne | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781402083631 |
| -- |
978-1-4020-8363-1 |
| 024 7# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
10.1007/978-1-4020-8363-1 |
| Source of number or code |
doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Pavlov, Andrei. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
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| Title |
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies |
| Medium |
[electronic resource] : |
| Remainder of title |
Process-Aware SRAM Design and Test / |
| Statement of responsibility, etc |
by Andrei Pavlov, Manoj Sachdev. |
| 264 #1 - |
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Dordrecht : |
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Springer Netherlands, |
| -- |
2008. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
XVI, 194 p. |
| Other physical details |
online resource. |
| 336 ## - |
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| -- |
text |
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txt |
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rdacontent |
| 337 ## - |
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computer |
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c |
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rdamedia |
| 338 ## - |
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| -- |
online resource |
| -- |
cr |
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rdacarrier |
| 347 ## - |
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| -- |
text file |
| -- |
PDF |
| -- |
rda |
| 490 1# - SERIES STATEMENT |
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| Series statement |
Frontiers In Electronic Testing, |
| International Standard Serial Number |
0929-1296 ; |
| Volume number/sequential designation |
40 |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
and Motivation -- SRAM Circuit Design and Operation -- SRAM Cell Stability: Definition, Modeling and Testing -- Traditional SRAM Fault Models and Test Practices -- Techniques for Detection of SRAM Cells with Stability Faults -- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Memory management (Computer science). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Memory Structures. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Sachdev, Manoj. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
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| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Display text |
Printed edition: |
| International Standard Book Number |
9781402083624 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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| Uniform title |
Frontiers In Electronic Testing, |
| -- |
0929-1296 ; |
| Volume number/sequential designation |
40 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/978-1-4020-8363-1">http://dx.doi.org/10.1007/978-1-4020-8363-1</a> |
| 912 ## - |
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| -- |
ZDB-2-ENG |
