MARC details
000 -LEADER |
fixed length control field |
04077nam a22004695i 4500 |
001 - CONTROL NUMBER |
control field |
978-1-4020-8588-8 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
DE-He213 |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20170628033522.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
100301s2008 ne | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781402085888 |
-- |
978-1-4020-8588-8 |
024 7# - OTHER STANDARD IDENTIFIER |
Standard number or code |
10.1007/978-1-4020-8588-8 |
Source of number or code |
doi |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
TK7888.4 |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TJFC |
Source |
bicssc |
072 #7 - SUBJECT CATEGORY CODE |
Subject category code |
TEC008010 |
Source |
bisacsh |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Coussy, Philippe. |
Relator term |
editor. |
245 10 - TITLE STATEMENT |
Title |
High-Level Synthesis |
Medium |
[electronic resource] : |
Remainder of title |
From Algorithm to Digital Circuit / |
Statement of responsibility, etc |
edited by Philippe Coussy, Adam Morawiec. |
264 #1 - |
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Dordrecht : |
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Springer Netherlands, |
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2008. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XV, 297 p. |
Other physical details |
online resource. |
336 ## - |
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text |
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txt |
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rdacontent |
337 ## - |
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computer |
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c |
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rdamedia |
338 ## - |
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online resource |
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cr |
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rdacarrier |
347 ## - |
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text file |
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PDF |
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rda |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
User Needs -- High-Level Synthesis: A Retrospective -- Catapult Synthesis: A Practical Introduction to Interactive C Synthesis -- Algorithmic Synthesis Using PICO -- High-Level SystemC Synthesis with Forte's Cynthesizer -- AutoPilot: A Platform-Based ESL Synthesis System -- “All-in-C” Behavioral Synthesis and Verification with CyberWorkBench -- Bluespec: A General-Purpose Approach to High-Level Synthesis Based on Parallel Atomic Transactions -- GAUT: A High-Level Synthesis Tool for DSP Applications -- User Guided High Level Synthesis -- Synthesis of DSP Algorithms from Infinite Precision Specifications -- High-Level Synthesis of Loops Using the Polyhedral Model -- Operation Scheduling: Algorithms and Applications -- Exploiting Bit-Level Design Techniques in Behavioural Synthesis -- High-Level Synthesis Algorithms for Power and Temperature Minimization. |
520 ## - SUMMARY, ETC. |
Summary, etc |
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools and approaches are required. The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse. This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. High-Level Synthesis: from Algorithm to Digital Circuit should be on each designer’s and CAD developer’s shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Logic design. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer science. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Systems engineering. |
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Circuits and Systems. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Processor Architectures. |
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Logic Design. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Morawiec, Adam. |
Relator term |
editor. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Display text |
Printed edition: |
International Standard Book Number |
9781402085871 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/978-1-4020-8588-8">http://dx.doi.org/10.1007/978-1-4020-8588-8</a> |
912 ## - |
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ZDB-2-ENG |