Processor and System-on-Chip Simulation (Record no. 15772)

MARC details
000 -LEADER
fixed length control field 03957nam a22004455i 4500
001 - CONTROL NUMBER
control field 978-1-4419-6175-4
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170628033549.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 130531s2010 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781441961754
-- 978-1-4419-6175-4
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-1-4419-6175-4
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.4
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJFC
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC008010
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Leupers, Rainer.
Relator term editor.
245 10 - TITLE STATEMENT
Title Processor and System-on-Chip Simulation
Medium [electronic resource] /
Statement of responsibility, etc edited by Rainer Leupers, Olivier Temam.
264 #1 -
-- Boston, MA :
-- Springer US :
-- Imprint: Springer,
-- 2010.
300 ## - PHYSICAL DESCRIPTION
Extent XIII, 345 p.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note System Simulation and Exploration -- The Life Cycle of a Virtual Platform -- Full-System Simulation from Embedded to High-Performance Systems -- Toward the Datacenter: Scaling Simulation Up and Out -- Modular ISA-Independent Full-System Simulation -- Structural Simulation for Architecture Exploration -- Fast Simulation -- Accelerating Simulation with FPGAs -- Scalable Simulation for MPSoC Software and Architectures -- Adaptive High-Speed Processor Simulation -- Representative Sampling Using SimPoint -- Statistical Sampling -- Efficient Cache Modeling with Sparse Data -- Statistical Simulation -- Impact of Silicon Technology -- Memory Modeling with CACTI -- Thermal Modeling for Processors and Systems-on-Chip -- Rapid Technology-Aware Design Space Exploration for Embedded Heterogeneous Multiprocessors -- Embedded Systems Simulation -- IP Modeling and Verification -- Configurable, Extensible Processor System Simulation -- Simulation Acceleration in Wireless Baseband Processing -- Trace-Driven Workload Simulation for MPSoC Software Performance Estimation.
520 ## - SUMMARY, ETC.
Summary, etc Processor and System-on-Chip Simulation Edited by: Rainer Leupers Olivier Temam The current trend from monolithic processors to multicore and multiprocessor systems on chips (MPSoC) with tens of cores and gigascale integration makes hardware architecture and software design more and more complex and costly. Therefore, simulation technology has become an extremely important pre-silicon verification and optimization vehicle. Simulation of computer architectures has made rapid progress recently. The primary application areas are hardware/software performance estimation and optimization, as well as functional and timing verification. Recent, innovative technologies, such as retargetable simulator generation, dynamic binary translation and sampling simulation have enabled widespread use of processor and system-on-chip (SoC) simulation tools in the semiconductor and embedded system industries. This book presents and discusses the principle technologies and state-of-the-art in high-level architecture software simulation, both at the processor and the system-on-chip level. • Presents state-of-the-art and future trends in processor and SoC simulation; • Demonstrates how simulation helps to boost hardware and software design productivity; • Addresses simulation requirements and technologies in the multicore context; • Covers system aspects, such as virtual platforms, bus simulation, caches, power, and design space exploration.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer aided design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Systems engineering.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer-Aided Engineering (CAD, CAE) and Design.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Temam, Olivier.
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9781441961747
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://dx.doi.org/10.1007/978-1-4419-6175-4">http://dx.doi.org/10.1007/978-1-4419-6175-4</a>
912 ## -
-- ZDB-2-ENG
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Source of acquisition Total Checkouts Barcode Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Central Library Central Library 28/06/2017 Springer EBook   E-38951 28/06/2017 28/06/2017 E-Book

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