The Power of Assertions in SystemVerilog (Record no. 15801)

MARC details
000 -LEADER
fixed length control field 03833nam a22004815i 4500
001 - CONTROL NUMBER
control field 978-1-4419-6600-1
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170628033552.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 101013s2010 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781441966001
-- 978-1-4419-6600-1
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-1-4419-6600-1
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.4
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJFC
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC008010
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Cerny, Eduard.
Relator term author.
245 14 - TITLE STATEMENT
Title The Power of Assertions in SystemVerilog
Medium [electronic resource] /
Statement of responsibility, etc by Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny.
250 ## - EDITION STATEMENT
Edition statement First.
264 #1 -
-- Boston, MA :
-- Springer US :
-- Imprint: Springer,
-- 2010.
300 ## - PHYSICAL DESCRIPTION
Extent XVII, 544 p. 166 illus.
Other physical details online resource.
336 ## -
-- text
-- txt
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-- computer
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-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Opening -- SystemVerilog Language and Simulation Semantics Overview -- Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Let Sequence and Property Declarations Inference -- Advanced Properties -- Advanced Sequences -- to Assertion Based Formal Verification -- Formal Verification and Models -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Formal Semantics -- Checkers and Assertion Libraries -- Checkers -- Checkers in Formal Verification -- Checker Libraries -- Future Enhancements.
520 ## - SUMMARY, ETC.
Summary, etc The Power of Assertions in SystemVerilog is a comprehensive book that enables the reader to reap the full benefits of assertion-based verification in the quest to abate hardware verification cost. The book is divided into three parts. The first part introduces assertions, SystemVerilog and its simulation semantics. The second part delves into the details of assertions and their semantics. All property operators, in conjunction with ease-of-use features and examples, are discussed to illustrate the immense expressive power of the language. The third part presents an extended description of checkers and a methodology for building reusable checker libraries. The book concludes by outlining some desirable future enhancements. Detailed descriptions of the language features are provided throughout the book, along with their uses and how they play together to construct powerful sets of property checkers. The exposition of the features is supplemented with examples that take the reader step-by-step, from intuitive comprehension to much greater depth of understanding, enabling the reader to become an expert user. A unique aspect of the book is that it is oriented toward both simulation and formal verification. The semantics is discussed in terms of both simulation events and formal definition. This blended approach imparts profound conceptual and practical guidance for a broader spectrum of readers. The Power of Assertions in SystemVerilog is a valuable reference for design engineers, verification engineers, tool builders and educators.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer engineering.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Systems engineering.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electrical Engineering.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Dudani, Surrendra.
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Havlicek, John.
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Korchemny, Dmitry.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9781441965998
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://dx.doi.org/10.1007/978-1-4419-6600-1">http://dx.doi.org/10.1007/978-1-4419-6600-1</a>
912 ## -
-- ZDB-2-ENG
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Source of acquisition Total Checkouts Barcode Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Central Library Central Library 28/06/2017 Springer EBook   E-38980 28/06/2017 28/06/2017 E-Book

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