MARC details
| 000 -LEADER |
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| fixed length control field |
03855nam a22004575i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-1-4419-9359-5 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20170628033610.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
110517s2011 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781441993595 |
| -- |
978-1-4419-9359-5 |
| 024 7# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
10.1007/978-1-4419-9359-5 |
| Source of number or code |
doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
|---|
| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Kundu, Sudipta. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
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| Title |
High-Level Verification |
| Medium |
[electronic resource] : |
| Remainder of title |
Methods and Tools for Verification of System-Level Designs / |
| Statement of responsibility, etc |
by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta. |
| 264 #1 - |
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| -- |
New York, NY : |
| -- |
Springer New York, |
| -- |
2011. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
XIII, 167 p. |
| Other physical details |
online resource. |
| 336 ## - |
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| -- |
text |
| -- |
txt |
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rdacontent |
| 337 ## - |
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| -- |
computer |
| -- |
c |
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rdamedia |
| 338 ## - |
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| -- |
online resource |
| -- |
cr |
| -- |
rdacarrier |
| 347 ## - |
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| -- |
text file |
| -- |
PDF |
| -- |
rda |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Introduction -- Related Work -- Background -- Execution-based Model Checking for High-Level Designs -- Efficient Symbolic Analysis for Concurrent Programs -- Translation Validation of High-Level Synthesis -- Parameterized Program Equivalence Checking -- Conclusions and Future Work. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence the topic area is also referred to as system level verification. Since such descriptions can also capture software, especially device drivers or other embedded software, this book will be of interest to both hardware and software designers. � The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification; Uses a combination of formal techniques to do scalable verification of system designs completely automatically; Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL; Written by researchers working in mainstream hardware and software design and includes results from both academia and industry � � � |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Computer aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Lerner, Sorin. |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Gupta, Rajesh K. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9781441993588 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/978-1-4419-9359-5">http://dx.doi.org/10.1007/978-1-4419-9359-5</a> |
| 912 ## - |
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ZDB-2-ENG |
