MARC details
| 000 -LEADER |
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03013nam a22004575i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-3-319-02378-6 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20170628034045.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
131115s2014 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9783319023786 |
| -- |
978-3-319-02378-6 |
| 024 7# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
10.1007/978-3-319-02378-6 |
| Source of number or code |
doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
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| Classification number |
TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TJFC |
| Source |
bicssc |
| 072 #7 - SUBJECT CATEGORY CODE |
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| Subject category code |
TEC008010 |
| Source |
bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Noia, Brandon. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
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| Title |
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc |
by Brandon Noia, Krishnendu Chakrabarty. |
| 264 #1 - |
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Cham : |
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Springer International Publishing : |
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Imprint: Springer, |
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2014. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
XVIII, 245 p. 133 illus., 115 illus. in color. |
| Other physical details |
online resource. |
| 336 ## - |
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text |
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txt |
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rdacontent |
| 337 ## - |
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computer |
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c |
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rdamedia |
| 338 ## - |
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online resource |
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cr |
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rdacarrier |
| 347 ## - |
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text file |
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PDF |
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rda |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. • Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; • Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; • Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Computer science. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Semiconductors. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Chakrabarty, Krishnendu. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
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| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Display text |
Printed edition: |
| International Standard Book Number |
9783319023779 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/978-3-319-02378-6">http://dx.doi.org/10.1007/978-3-319-02378-6</a> |
| 912 ## - |
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ZDB-2-ENG |
