Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (Record no. 22402)

MARC details
000 -LEADER
fixed length control field 07165nam a22005535i 4500
001 - CONTROL NUMBER
control field 978-3-540-95948-9
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170628035000.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
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fixed length control field 100301s2009 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540959489
-- 978-3-540-95948-9
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-3-540-95948-9
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.L63
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYF
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM036000
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Svensson, Lars.
Relator term editor.
245 10 - TITLE STATEMENT
Title Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Medium [electronic resource] :
Remainder of title 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers /
Statement of responsibility, etc edited by Lars Svensson, José Monteiro.
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg,
-- 2009.
300 ## - PHYSICAL DESCRIPTION
Extent XIII, 462 p.
Other physical details online resource.
336 ## -
-- text
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-- rdacontent
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-- computer
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-- rdamedia
338 ## -
-- online resource
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347 ## -
-- text file
-- PDF
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490 1# - SERIES STATEMENT
Series statement Lecture Notes in Computer Science,
International Standard Serial Number 0302-9743 ;
Volume number/sequential designation 5349
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope.
520 ## - SUMMARY, ETC.
Summary, etc This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer science.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Memory management (Computer science).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer system performance.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Systems engineering.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Science.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Processor Architectures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element System Performance and Evaluation.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Arithmetic and Logic Structures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Memory Structures.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and Systems.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Monteiro, José.
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9783540959472
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Lecture Notes in Computer Science,
-- 0302-9743 ;
Volume number/sequential designation 5349
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://dx.doi.org/10.1007/978-3-540-95948-9">http://dx.doi.org/10.1007/978-3-540-95948-9</a>
912 ## -
-- ZDB-2-SCS
912 ## -
-- ZDB-2-LNC
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Source of acquisition Total Checkouts Barcode Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Central Library Central Library 28/06/2017 Springer EBook   E-45581 28/06/2017 28/06/2017 E-Book

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