Logic Synthesis for FSM-Based Control Units (Record no. 23061)

MARC details
000 -LEADER
fixed length control field 04962nam a22005655i 4500
001 - CONTROL NUMBER
control field 978-3-642-04309-3
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20170628035121.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2009 gw | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783642043093
-- 978-3-642-04309-3
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-3-642-04309-3
Source of number or code doi
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7800-8360
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7874-7874.9
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJF
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC008000
Source bisacsh
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC008070
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.381
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Barkalov, Alexander.
Relator term author.
245 10 - TITLE STATEMENT
Title Logic Synthesis for FSM-Based Control Units
Medium [electronic resource] /
Statement of responsibility, etc by Alexander Barkalov, Larysa Titarenko.
264 #1 -
-- Berlin, Heidelberg :
-- Springer Berlin Heidelberg,
-- 2009.
300 ## - PHYSICAL DESCRIPTION
Extent XIX, 233 p.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
490 1# - SERIES STATEMENT
Series statement Lecture Notes in Electrical Engineering,
International Standard Serial Number 1876-1100 ;
Volume number/sequential designation 53
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Hardwired Interpretation of Control Algorithms -- Matrix Realization of Control Units -- Evolution of Programmable Logic -- Optimization for Logic Circuit of Mealy FSM -- Optimization for Logic Circuit of Moore FSM -- FSM Synthesis with Transformation of GSA -- FSM Synthesis with Object Code Transformation -- FSM Synthesis with Elementary Chains -- Conclusion.
520 ## - SUMMARY, ETC.
Summary, etc The control unit is one of the most important parts of any digital system responsible for interplay of other system blocks. Very often, the model of a finite state machine (FSM) is used to represent the behaviour of a control unit. Modern computer-aided design tools include a lot of optimal solutions (library cells) for implementation of such regular blocks of digital systems as decoders, multiplexers, parallel multibit adders and so on. But as a rule, control units have an irregular structure which makes impossible to design their logic circuits using the standard library cells. To use these cells, an FSM can be represented by a multilevel model based on the principle of structural decomposition. In multilevel models, for example, multiplexers are used to replace logical conditions, decoders are used to implement microoperations, and different memory blocks are used to transform object codes. Design methods depend strongly on such factors as an FSM model in use, specific features of logic elements implementing its logic circuit, characteristics of a control algorithm to be interpreted. In the case of Moore FSM, optimization methods are based on existence of the classes of pseudoequivalent states. Their use permits to compress the transition table of Moore FSM till the size of the table for equivalent Mealy FSM. In the case of Mealy FSM, optimization methods are based on transformation of either object codes, or interpreted graph-schemes of algorithm. In the case of CPLD, the hardware decrease can be achieved using more than single source of state codes. In the case of FPGA, the structural decomposition allows using embedded memory blocks for implementation of decoding logic. In case of ASIC, design methods target on minimization of the chip area occupied by an FSM circuit. It can be achieved due to use of different encoding methods, where both internal states and collections of microoperations can be encoded. If a control algorithm is a linear one, then a state register of Moore FSM can be replaced by a counter. It leads to simplification of the input memory functions and, in turns, to the hardware amount decrease. The book includes a lot of design methods targeted on logic synthesis of both Mealy and Moore FSMs, where their logic circuits can be implemented using ASIC, as well as CPLD or FPGA. The most of discussed methods belong to the authors of this book. This book will be interesting and useful for students and postgraduates in the area of Computer Science, as well as for designers of digital systems included complex control units. Proposed models and design methods open new possibilities for creating logic circuits of control units with optimal hardware amount.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Microprogramming.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Mathematics.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electronics.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Systems engineering.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electronics and Microelectronics, Instrumentation.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Control Structures and Microprogramming.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Logic Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Applications of Mathematics.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Titarenko, Larysa.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9783642043086
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Lecture Notes in Electrical Engineering,
-- 1876-1100 ;
Volume number/sequential designation 53
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://dx.doi.org/10.1007/978-3-642-04309-3">http://dx.doi.org/10.1007/978-3-642-04309-3</a>
912 ## -
-- ZDB-2-ENG
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Source of acquisition Total Checkouts Barcode Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Central Library Central Library 28/06/2017 Springer EBook   E-46240 28/06/2017 28/06/2017 E-Book

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