CMOS PLL Synthesizers: Analysis and Design [electronic resource] / by Keliu Shu, Edgar Sánchez-Sinencio.
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
- text
- computer
- online resource
- 9780387236698
- 621.3 23
- TK1-9971
Item type | Current library | Call number | Status | Date due | Barcode | |
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Central Library | Available | E-37451 |
Frequency Synthesizer for Wireless Applications -- PLL Frequency Synthesizer -- ?? Fractional-N PLL Synthesizer -- Enhanced Phase Switching Prescaler -- Loop Filter with Capacitance Multiplier -- Other Building Blocks of PLL -- Prototype Measurement Results -- Conclusions.
CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer. This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers.
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