SAT-Based Scalable Formal Verification Solutions [electronic resource] / by Malay K. Ganai, Aarti Gupta.

Design Verification Challenges -- Design Verification Challenges -- Background -- Basic Infrastructure -- Efficient Boolean Representation -- Hybrid DPLL-Style SAT Solver -- Falsification -- SAT-Based Bounded Model Checking -- Distributed SAT-Based BMC -- Efficient Memory Modeling in BMC -- BMC for Multi-Clock Systems -- Proof Methods -- Proof by Induction -- Unbounded Model Checking -- Abstraction/Refinement -- Proof-Based Iterative Abstraction -- Verification Procedure -- SAT-Based Verification Framework -- Synthesis for Verification.

Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors’ practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products.