Low-Power Variation-Tolerant Design in Nanometer Silicon [electronic resource] / edited by Swarup Bhunia, Saibal Mukhopadhyay.

Introduction and Motivation -- Background on Power Dissipation -- Background on Parameter Variations -- Low power Logic Design under Variations -- Low Power Memory Design under Variations -- System and Architecture Level Design -- Emerging Challenges and Solution Approach -- Conclusion and Discussion.

Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. Coverage includes logic and memory design, modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. •Introduces readers to some of the most important challenges in low-power and variation-tolerant IC design in nanoscale technologies; •Presents a holistic view of Low-Power Variation-Tolerant Design, at different levels of design abstraction, starting from device to circuit, architecture and system; •Offers comprehensive coverage of modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems, micro-architecture, DSP, mixed-signal and FPGAs, including current industrial practices, technology scaling trends, and emerging challenges; •Describes in detail modeling and analysis of different variation effects (die-to-die and within-die, process and temporal) on low-power designs; Includes coverage of ultra low-power and robust sub-threshold design.