TY  - BOOK
AU  - Mishra,Prabhat
AU  - Dutt,Nikil D.
ED  - SpringerLink (Online service)
TI  - Functional Verification of Programmable Embedded Architectures: A Top-Down Approach 
SN  - 9780387263991
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2005///
CY  - Boston, MA
PB  - Springer US
KW  - Engineering
KW  - Computer science
KW  - Software engineering
KW  - Computer system performance
KW  - Computer aided design
KW  - Systems engineering
KW  - Circuits and Systems
KW  - Processor Architectures
KW  - Special Purpose and Application-Based Systems
KW  - Computer-Aided Engineering (CAD, CAE) and Design
KW  - System Performance and Evaluation
KW  - Electronic and Computer Engineering
N1  - to Functional Verification -- Architecture Specification -- Architecture Specification -- Validation of Specification -- Top-Down Validation -- Executable Model Generation -- Design Validation -- Functional Test Generation -- Future Directions -- Conclusions
N2  - Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems
UR  - http://dx.doi.org/10.1007/b137514
ER  -