TY  - BOOK
AU  - DasGupta,Pallab
ED  - SpringerLink (Online service)
TI  - A Roadmap for Formal Property Verification
SN  - 9781402047589
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2006///
CY  - Dordrecht
PB  - Springer Netherlands
KW  - Engineering
KW  - Logic design
KW  - Computer science
KW  - Computer aided design
KW  - Electronics
KW  - Systems engineering
KW  - Circuits and Systems
KW  - Computer-Aided Engineering (CAD, CAE) and Design
KW  - Electronics and Microelectronics, Instrumentation
KW  - Logic Design
KW  - Electronic and Computer Engineering
KW  - Mathematical Logic and Formal Languages
N1  - Languages for Temporal Properties -- How Does the Property Checker Work? -- Is My Specification Consistent? -- Have I Written Enough Properties? -- Design Intent Coverage -- Test Generation Games -- A Roadmap for Formal Property Verification
N2  - Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples – you do not need any background on formal methods to read most parts of this book
UR  - http://dx.doi.org/10.1007/978-1-4020-4758-9
ER  -