TY  - BOOK
AU  - Torquati,Massimo
AU  - Bertels,Koen
AU  - Karlsson,Sven
AU  - Pacull,François
ED  - SpringerLink (Online service)
TI  - Smart Multicore Embedded Systems
SN  - 9781461488002
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2014///
CY  - New York, NY
PB  - Springer New York, Imprint: Springer
KW  - Engineering
KW  - Computer science
KW  - Electronics
KW  - Systems engineering
KW  - Circuits and Systems
KW  - Processor Architectures
KW  - Electronics and Microelectronics, Instrumentation
N1  - Introduction -- Part I Parallel Programming Models and Methodologies -- Parallel Programming Models -- Compilation Tool Chains and Intermediate Representations -- Part II HW/SW Architectures Concepts -- The STHORM Platform -- The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Co-Processor (ASVP) -- Part III Run-time and Faults Management -- Fault Tolerance -- Introduction to Dynamic Code Generation -- an Experiment with Matrix Multiplication for STHORM Platform -- Part IV Case Studies -- Signal Processing: Radar -- Image Processing: Object Recognition -- Video Processing: Foreground Recognition in the ASVP platform
N2  - This book provides a single-source reference to the state-of-the-art of high-level programming models and compilation tool-chains for embedded system platforms. The authors address challenges faced by programmers developing software to implement parallel applications in embedded systems, where very often they are forced to rewrite sequential programs into parallel software, taking into account all the low level features and peculiarities of the underlying platforms. Readers will benefit from these authors’ approach, which takes into account both the application requirements and the platform specificities of various embedded systems from different industries. Parallel programming tool-chains are described that take as input parameters both the application and the platform model, then determine relevant transformations and mapping decisions on the concrete platform, minimizing user intervention and hiding the difficulties related to the correct and efficient use of memory hierarchy and low level code generation
UR  - http://dx.doi.org/10.1007/978-1-4614-8800-2
ER  -