TY  - BOOK
AU  - Mandal,Ayan
AU  - Khatri,Sunil P.
AU  - Mahapatra,Rabi
ED  - SpringerLink (Online service)
TI  - Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling 
SN  - 9781461494058
AV  - TK7888.4 
U1  - 621.3815 23
PY  - 2014///
CY  - New York, NY
PB  - Springer New York, Imprint: Springer
KW  - Engineering
KW  - Computer science
KW  - Electronics
KW  - Systems engineering
KW  - Circuits and Systems
KW  - Processor Architectures
KW  - Electronics and Microelectronics, Instrumentation
N1  - Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work
N2  - This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art
UR  - http://dx.doi.org/10.1007/978-1-4614-9405-8
ER  -