000 | 03518nam a22005295i 4500 | ||
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001 | 978-0-387-26399-1 | ||
003 | DE-He213 | ||
005 | 20170628033247.0 | ||
007 | cr nn 008mamaa | ||
008 | 100301s2005 xxu| s |||| 0|eng d | ||
020 |
_a9780387263991 _9978-0-387-26399-1 |
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024 | 7 |
_a10.1007/b137514 _2doi |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aMishra, Prabhat. _eauthor. |
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245 | 1 | 0 |
_aFunctional Verification of Programmable Embedded Architectures _h[electronic resource] : _bA Top-Down Approach / _cby Prabhat Mishra, Nikil D. Dutt. |
264 | 1 |
_aBoston, MA : _bSpringer US, _c2005. |
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300 |
_aXIX, 180 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _ato Functional Verification -- Architecture Specification -- Architecture Specification -- Validation of Specification -- Top-Down Validation -- Executable Model Generation -- Design Validation -- Functional Test Generation -- Future Directions -- Conclusions. | |
520 | _aValidation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aComputer science. | |
650 | 0 | _aSoftware engineering. | |
650 | 0 | _aComputer system performance. | |
650 | 0 | _aComputer aided design. | |
650 | 0 | _aSystems engineering. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aSpecial Purpose and Application-Based Systems. |
650 | 2 | 4 | _aComputer-Aided Engineering (CAD, CAE) and Design. |
650 | 2 | 4 | _aSystem Performance and Evaluation. |
650 | 2 | 4 | _aElectronic and Computer Engineering. |
700 | 1 |
_aDutt, Nikil D. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9780387261430 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/b137514 |
912 | _aZDB-2-ENG | ||
999 |
_c14368 _d14368 |