000			03723nam a22005055i 4500
001			978-0-387-48550-8
003			DE-He213
005			20170628033321.0
007			cr nn 008mamaa
008			100301s2007 xxu| s |||| 0|eng d
020			_a9780387485508 _9978-0-387-48550-8
024	7		_a10.1007/0-387-48550-3 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aSaxena, Prashant. _eauthor.
245	1	0	_aRouting Congestion in VLSI Circuits: Estimation and Optimization _h[electronic resource] / _cby Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar.
264		1	_aBoston, MA : _bSpringer US, _c2007.
300			_aXIV, 250 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aSeries on Integrated Circuits and Systems, _x1558-9412
505	0		_aThe Origins of Congestion -- An Introduction to Routing Congestion -- The Estimation of Congestion -- Placement-level Metrics for Routing Congestion -- Synthesis-level Metrics for Routing Congestion -- The Optimization of Congestion -- Congestion Optimization During Interconnect Synthesis and Routing -- Congestion Optimization During Placement -- Congestion Optimization During Technology Mapping and Logic Synthesis -- Congestion Implications of High Level Design.
520			_aWith the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware. Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design. Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aTelecommunication.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
650	2	4	_aCommunications Engineering, Networks.
700	1		_aShelar, Rupesh S. _eauthor.
700	1		_aSapatnekar, Sachin S. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387300375
830		0	_aSeries on Integrated Circuits and Systems, _x1558-9412
856	4	0	_uhttp://dx.doi.org/10.1007/0-387-48550-3
912			_aZDB-2-ENG
999			_c14636 _d14636