000			03833nam a22004815i 4500
001			978-1-4419-6600-1
003			DE-He213
005			20170628033552.0
007			cr nn 008mamaa
008			101013s2010 xxu| s |||| 0|eng d
020			_a9781441966001 _9978-1-4419-6600-1
024	7		_a10.1007/978-1-4419-6600-1 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aCerny, Eduard. _eauthor.
245	1	4	_aThe Power of Assertions in SystemVerilog _h[electronic resource] / _cby Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny.
250			_aFirst.
264		1	_aBoston, MA : _bSpringer US : _bImprint: Springer, _c2010.
300			_aXVII, 544 p. 166 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aOpening -- SystemVerilog Language and Simulation Semantics Overview -- Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Let Sequence and Property Declarations Inference -- Advanced Properties -- Advanced Sequences -- to Assertion Based Formal Verification -- Formal Verification and Models -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Formal Semantics -- Checkers and Assertion Libraries -- Checkers -- Checkers in Formal Verification -- Checker Libraries -- Future Enhancements.
520			_aThe Power of Assertions in SystemVerilog is a comprehensive book that enables the reader to reap the full benefits of assertion-based verification in the quest to abate hardware verification cost. The book is divided into three parts. The first part introduces assertions, SystemVerilog and its simulation semantics. The second part delves into the details of assertions and their semantics. All property operators, in conjunction with ease-of-use features and examples, are discussed to illustrate the immense expressive power of the language. The third part presents an extended description of checkers and a methodology for building reusable checker libraries. The book concludes by outlining some desirable future enhancements. Detailed descriptions of the language features are provided throughout the book, along with their uses and how they play together to construct powerful sets of property checkers. The exposition of the features is supplemented with examples that take the reader step-by-step, from intuitive comprehension to much greater depth of understanding, enabling the reader to become an expert user. A unique aspect of the book is that it is oriented toward both simulation and formal verification. The semantics is discussed in terms of both simulation events and formal definition. This blended approach imparts profound conceptual and practical guidance for a broader spectrum of readers. The Power of Assertions in SystemVerilog is a valuable reference for design engineers, verification engineers, tool builders and educators.
650		0	_aEngineering.
650		0	_aComputer engineering.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectrical Engineering.
700	1		_aDudani, Surrendra. _eauthor.
700	1		_aHavlicek, John. _eauthor.
700	1		_aKorchemny, Dmitry. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441965998
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-6600-1
912			_aZDB-2-ENG
999			_c15801 _d15801